The present disclosure relates to a structure for chip assembly, and particularly to a method of assembling semiconductor chips with coreless substrates employing a patterned adhesive layer, and structures for effecting the same.
A coreless substrate is a substrate without a core, which includes a thick stiff material having enough mechanical strength to provide support for additional layers thereupon. Because of the lack of a core, a coreless substrate offers lower cost, enhanced wireability, and performance advantages over cored substrates, making them very attractive for packaging purposes.
However, the coreless substrate introduces additional difficulties during packaging. Specifically, coreless substrates warp during the assembly with a chip, which can be a semiconductor chip that is bonded to the coreless substrate through a flip chip assembly process. To alleviate the problem of warpage during the assembly, some solutions have been proposed in the art.
A first prior art method utilizes a dedicated clamp fixture which holds coreless substrates during assembly. While the clamp fixture may be reused for multiple coreless substrates, the clamp fixture must be adjusted not only for each coreless substrate size, but for temperature changes that are needed to bond chips to the coreless substrate. A second prior art method utilizes a removable planar adhesive layer applied to the entirety of the back side of a coreless substrate. A temporary stiffener is attached to the coreless substrate through the removable planar adhesive layer. The removal process for the “removable” planar adhesive layer after saw-singulation (dicing) can be difficult and time consuming. A third prior art method utilizes solder structures to provide temporary bonding between a coreless substrate and a stiffener. The third prior art method is time consuming and expensive due to the many processing steps required for attaching and detaching solder balls between the coreless substrate and the stiffener.